A cache is a relatively small, high speed memory that is used to increase the speed of a data processing system. The access time of the cache is about the same as a central processing unit (CPU) logic propagation delay. The cache stores frequently used instructions or data to reduce the number of accesses between the CPU and a relatively slower main memory, thus improving system performance.
A cache TAG RAM is frequently used to increase the performance of the cache. The cache TAG RAM receives an address that is provided by the processor and determines if the requested instructions or data are present in the cache memory. Like the cache, the cache TAG RAM has an array of conventional static random access memory (SRAM) cells. A cache TAG RAM typically has two operating modes: write mode; and read/compare mode. When data is written into the cache memory, the higher order bits of the address of the data are stored in the TAG array. When in the read/compare mode, the cache TAG RAM has a comparator that compares a processor generated address to the TAG address. If the TAG address and the processor generated address are the same, a cache "hit" occurs, and a match signal of a predetermined logic state is provided by the cache TAG RAM, indicating that the requested data is located in the cache memory. If the processor generated address and the TAG address are not the same, a cache "miss" occurs, and a match signal of an opposite logic state is provided by the cache TAG RAM, indicating that the requested data is not located in the cache memory.
It is important for the match signal to be generated as quickly as possible after the cache TAG comparator receives the data to be compared. In a prior art cache TAG RAM, the read mode and the compare mode generally share the same data path. FIG. 1 illustrates in block diagram form, a cache TAG RAM 10 in accordance with the prior art. Cache TAG RAM 10 includes a TAG array 11, row decoding 12, column decoding 13, level shifting circuits 14 and 15, sense amplifiers 16 and 17, exclusive OR circuits 18 and 19, and reduction circuit 20. Cache TAG RAM I0 receives address bits labeled "AD.sub.0 " through "AD.sub.M ". Address bits AD.sub.0 -AD.sub.N include the most significant bits of the address, and address bits AD.sub.N+1 -AD.sub.M are the least significant bits of the address. In response to receiving address signals AD.sub.N+1 -AD.sub.M, TAG array 11 provides differential data signals DIF.sub.0 /DIF.sub.0 * through DIF.sub.N /DIF.sub.N *. Note that an asterisk (*) after a signal name indicates that the signal is a logical complement of a signal having the same name but lacking the asterisk (*). Differential data signals DIF.sub.0 /DIF.sub.0 * through DIF.sub.N /DIF.sub.N * are level shifted and amplified. Exclusive OR circuits 18 and 19 are used to compare data signals DATA.sub.0 through DATA.sub.N to address bits AD.sub.0 -AD.sub.N. If all of exclusive OR circuits 18 and 19 provide a match signal indicating the TAG address stored in TAG array 11 is the same as the address of the requested data, then a HIT signal is provided by reduction circuit 20. The cache memory (not shown in FIG. 1 ) provides the requested data or instructions to the data processing system.
Reduction circuit 20 of the prior art cache TAG RAM 10 typically compares the logic states of match signals MATCH.sub.0 through MATCH.sub.N to a reference voltage to determine a hit or a miss. The reference voltage is provided at a voltage level that is about half way between a logic high voltage and a logic low voltage of match signals MATCH.sub.0 through MATCH.sub.N. If the logic swing of match signals MATCH.sub.0 through MATCH.sub.N is relatively small, the accuracy of the reference voltage has to be maintained within a narrow margin, complicating circuit design.